1. Field of the Invention
The present invention relates to logic circuits, and more particularly, to a composite logic circuit that carries out logical operation for a logic signal having the logic level changing between a first potential and a second potential and a logic signal having the logic level changing between the first potential and a third potential.
2. Description of the Background Art
A composite logic circuit is conventionally used for carrying out a predetermined logical operation for applied logic signals having the logic level changing between a first potential and second potential and between the first potential and a third potential. In such a composite logic circuit, a logic signal having the logic level changing between a first potential and a third potential is converted into a logic signal having the logic signal changing between the first potential and a second potential by a level shifter, followed by a logical operation for two logic signals having the logic level changing between the first potential and the second potential.
FIG. 3 is a circuit diagram of a conventional composite logic circuit to which are provided a logic signal having the logic level changing between the first potential and a second potential and a logic signal having the logic level changing between the first potential and a third potential. This composite logic circuit includes a level shifter 21 and NOR gates 26 and 27.
A first logic signal Ia having the logic level changing between a first potential GND and a second potential VEE under the relationship of VEE&gt;GND is supplied to a first input node 41. A second logic signal Ib having the logic level changing between the first potential GND and a third potential VDD under the relationship of VDD&gt;GND is supplied to a second input node 42, A third logic signal /Ib which is an inverted signal of the second logic signal Ib is supplied to a third input node 43.
A first output node 51 provides a first output signal Oa representing the NOR result of first and second logic signals Ia and Ib. A second output node 52 provides a second output signal Ob representing the NOR result of first and third logic signals Ia and /Ib.
Level shifter 21 converts second and third logic signals Ib and /Ib having their logic levels changing between the first potential GND and the third potential VDD into a logic signal c and a logic signal /c which is an inverted signal thereof having the logic levels changing between the first potential GND and the second potential VEE.
Level shifter 21 includes transistors 22 and 23 which are P channel MOS-FETs, and transistors 24 and 25 which are N channel MOS-FETs. These transistors 22, 23, 24 and 25 are connected between a first power supply node 61 receiving the first potential GND and a second power supply node 62 receiving the second potential VEE.
Transistor 22 has its source connected to the second power supply node 62 and its drain connected to the drain of transistor 24. Transistor 23 has its source connected to the second power supply node 62 and its drain connected to the drain of transistor 25. Transistors 24 and 25 respectively have their sources connected to the first power supply node 61. Transistor 22 has its gate connected to the node between transistors 23 and 25. Transistor 23 has its gate connected to the node between transistors 22 and 24. Transistor 24 has its gate connected to the second input node 42. Transistor 25 has its gate connected to the third input node 43.
In such a level shifter 21, transistor 22 has its gate connected to one input terminal of NOR gate 26, and transistor 23 has its gate connected to one input terminal of NOR gate 27. This connection allows logic signal c to be provided from the gate of transistor 22 to NOR gate 26, and logic signal /c provided from the gate of transistor 23 to NOR gate 27.
The first input node 41 is connected to the other input terminal of NOR gate 26 and to the other input terminal of NOR gate 27. The first output node 51 is connected to the output terminal of NOR gate 26, and the second output node 52 is connected to the output terminal of NOR gate 27.
The operation of level shifter 21 will be described hereinafter. When the second logic signal Ib attains the level of the third potential VDD, transistor 24 is turned on, whereby the gate of transistor 23 attains the potential of the first potential GND. This causes transistor 23 to be turned on, whereby the gate of transistor 22 attains the potential of the second potential VEE. Here, transistor 25 is turned off due to the third logic signal /Ib attaining the level of the first potential GND, and transistor 22 is turned off due to the gate attaining the second potential VEE.
When third logic signal /Ib attains the level of the third potential VDD, transistor 25 is turned on, whereby the gate of transistor 22 attains the first potential GND. This turns on transistor 22, whereby the gate of transistor 23 attains the second potential VEE. Here, transistor 24 is turned off due to the second logic signal Ib attaining the level of the first potential GND, and transistor 23 is turned off due to its gate attaining the second potential VEE.
When the second logic signal Ib attains the level of the third potential VDD, and the third logic signal /Ib attains the level of the first potential GND, the respective gates in transistors 22 and 23 attain the level of the second potential VEE and the first potential GND, respectively, whereby logic signals c and /c attain the level of the second potential VEE and the first potential GND, respectively. When the second logic signal Ib attains the level of the first potential GND and the third logic signal /Ib attains the level of the third potential VDD, the respective gates of transistors 22 and 23 attain the first and second potentials GND and VEE, respectively, whereby logic signals c and /c attain the level of the first and second potentials GND and VEE, respectively.
Thus, level shifter 21 converts the level of the second and third logic signals Ib and /Ib into logic signals c and /c that change within a potential range identical to that of the first logic signal Ia.
NOR gates 26 and 27 will be described in details hereinafter.
NOR gates 26 and 27 have the same structure, and one NOR gate will be taken as an example. FIG. 4 is a circuit diagram showing the structure of each of NOR gates 26 and 27.
Each of NOR gates 26 and 27 includes transistors 28 and 29 which are P channel MOS-FETs, and transistors 30 and 31 which are N channel MOS-FETs. An input terminal A receives the logic signal c or /c. An input terminal B receives the first logic signal Ia. An output terminal C is connected to first output node 51 or second output node 52 shown in FIG. 3. Transistor 28 has its source connected to a second power supply node 62 and its drain connected to the source of transistors 29. Transistor 29 has its drain connected to the output terminal C. Transistors 30 and 31 have their drains connected to the output terminal C and their sources connected to the first power supply node 61.
Input terminal A is connected to the gates of transistors 28 and 30. Input terminal B is connected to the gates of transistors 29 and 31.
The operation of NOR gate shown in FIG. 4 will be described. When the logic signal c or /c and the first logic signal Ia both attain the level of the first potential GND, transistors 28 and 29 are both turned on and transistors 30 and 31 are both turned off, whereby the potential of the output terminal C attains the second potential VEE. Otherwise, either or both of transistors 28 and 29 are turned off and either or both of transistors 30 and 31 are turned on, whereby the potential of the output terminal C attains the level of the first potential GND.
Thus, a signal representing the NOR result between the logic signal c and the first logic signal Ia, i.e. a signal representing the NOR result between the second logic signal Ib and the first logic signal Ia is provided as a first output signal Oa from the output terminal C of NOR gate 26 via first output node 51. A signal representing the NOR result between the logic signal /c and the first logic signal Ia, i.e. a signal representing the NOR result between the third logic signal /Ib and the first logic signal Ia is provided as a second output signal Ob from the output terminal C of NOR gate 27 via second output node 52.
FIG. 5 is a truth table of the composite logic circuit of FIG. 3. The relationship between the input signal and the output signal in the composite logic circuit of FIG. 3 will be described with reference to FIG. 5. First, the first output signal Oa will be described. When the first and second logic signals Ia and Ib both attain the level of the first potential GND, the first output signal Oa attains the level of the second potential VEE. Otherwise, the first output signal Oa attains the level of the first potential GND.
Next, the second output signal will be described. When first and third logic signals Ia and /Ib both attain the level of the first potential GND, the second output signal Ob attains the level of the second potential VEE. Otherwise, the second output signal Ob attains the level of the first potential GND.
Thus, a total of 12 transistors was required in the composite logic signal of FIG. 3.
Another example of a conventional composite logic circuit will be described with reference to FIG. 6. In FIG. 6, components corresponding to those of the composite logic circuit of FIG. 3 have the same reference numerals denoted, and their description will not be repeated.
The composite logic circuit of FIG. 6 is similar to that of FIG. 3 except for NAND gates 32 and 33 substituted for NOR gates 26 and 27 of the composite logic circuit of FIG. 3. In the composite logic circuit of FIG. 6, an NAND operation between the first and second logic signals Ia and Ib and an NAND operation between the first and third logic signals Ia and /Ib are carried out. The respective operation results are provided as first and second output signals Oa and Ob, respectively.
NAND gates 32 and 33 will be described in details. Because NAND gate 32 and NAND gate 33 have identical structures, one of NAND gates 32 and 33 will be taken as an example.
Each of NAND gates 32 and 33 includes transistors 34 and 35 which are P channel MOS-FETs, and transistors 36 and 37 which are N channel MOS-FETs. Transistors 34 and 35 respectively have their sources connected to a second power supply node 62 and their drains connected to the output terminal C. Transistor 36 has its drain connected to the output terminal C and its source connected to the drain of transistor 37. Transistor 37 has its source connected to the first power supply node 61. Transistors 34 and 36 have their gates connected to input terminal A. Transistors 35 and 37 have their gates connected to the input terminal B.
The operation of the NAND gate of FIG. 7 will be described. When logic signal c or /c and the first logic signal Ia both attain the level of the second potential VEE, transistors 36 and 37 are both turned on and transistors 34 and 35 are both turned off. This brings the potential of the output terminal C to the level of the first potential GND. Otherwise, either or both of transistors 36 and 37 are turned on and either or both of transistors 34 and 35 are turned off, whereby the potential of the output terminal C attains the level of the second potential VEE.
Thus, a signal representing the NAND result between the logic signal c and the first logic signal Ia, i.e. a signal representing the NAND result between second and first logic signals Ib and Ia is provided as the first output signal Oa from the output terminal C of NAND gate 32 via the first output node 51. A signal representing the NAND result between the logic signal /c and the first logic signal Ia, i.e. a signal representing the NAND result between third and first logic signals /Ib and Ia is provided from the output terminal C of NAND gate 33 as the second output signal Ob via the second output node 52.
FIG. 8 shows the truth table of the composite logic circuit of FIG. 6. The relationship between the input signal and the output signal of the composite logic circuit of FIG. 6 will be described with reference to FIG. 8. The first output signal Oa will be described first. When the first logic signal Ia attains the level of second potential VEE and the second logic signal Ib attains the level of the third potential VDD, the first output signal Oa is brought to the level of the first potential GND. Otherwise, the first output signal Oa is brought to the level of the second potential VEE.
The second output signal Ob will be described. When the first logic signal Ia attains the level of the second potential VEE, and the third logic signal /Ib attains the level of the third potential VDD, the second output signal Ob is brought to the level of the first potential GND. Otherwise, the second output signal Ob is brought to the level of the second potential VEE.
Thus, a total of 12 transistors is required in the composite logic circuit of FIG. 6.
As mentioned above, a conventional composite logic circuit such as those shown in FIGS. 3 and 6 require the great amount of 12 transistors. This requirement of many transistors in a conventional composite logic circuit resulted in a disadvantage of increasing the chip size when the circuit is implemented in an LSI.